40 cache opportunities in Santa Clara updated today
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· Page 1 / 2We are seeking an experienced Senior Cache Coherency Architect to join our ambitious team at NVIDIA. This opportunity allows you to be part of a world-class organization that develops scalable, low-latency, high-bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA produ
Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by cli
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and effi
In this role, you will contribute to the architecture of cache-coherent interconnect and cache subsystems, including architecture definition, modeling, and implementation. You will collaborate with CPU, GPU, memory subsystem, and SoC architects to define coherency solutions that integrate effectivel
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL codin
Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer le
Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer le
Nvidia CorporationWe are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on‑chip and off‑chip interconnect network, MP coherency and last‑level and system caches, focusing on tasks such as micro‑architectural definition, RTL codin
Nvidia CorporationA leading technology company in Santa Clara is seeking a Senior Logic Design Engineer to design CPU on-chip and off-chip interconnect networks. The role involves owning and delivering a chip unit, writing performant RTL, and collaborating closely with verification teams. Candidates should have a Mas
Apple Inc.Santa Clara, California, United States Hardware Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are pre
Apple Inc.Santa Clara, California, United States Hardware Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are pre
Apple Inc.A leading technology corporation in Santa Clara is seeking a seasoned hardware designer specializing in cache subsystems for high-performance systems on chip (SoC). The ideal candidate has over 10 years in ASIC design with expertise in memory systems. This role offers a competitive salary range of $
AppleRole Number: 200624401-3760 Summary Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with
Santa Clara, California, United States Hardware Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are pre
AppleRole Number: 200628798-3760 Summary Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working peo
AppleRole Number: 200624401-3760 Summary Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with
Santa Clara, California, United States Hardware Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard
AppleRole Number: 200647235-3760 Summary Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products
A leading technology company is seeking an experienced CPU Cache Microarchitect/RTL Engineer to drive CPU multi-level cache subsystem architecture and RTL development. The ideal candidate will possess a minimum of a Bachelor's degree alongside at least 3 years of industry experience in microprocesso
A leading technology company in California is looking for an experienced professional to handle ASIC design verification for various processing blocks within a System on Chip (SoC). Candidates should hold a B.S. or M.S. degree in Computer Engineering or related field and possess over 8 years of expe
AppleImagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the in
MatXWhat MatX Is Building MatX is seeking engineers with strong Rust skills to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. You will write Rust tests that verify our software models and hardware design behave identically and match the specification. Your t
TecTamminaKnowledge of healthcare information technology at a level normally acquired through completion of a Bachelor’s degree with concentration in Computer Science or other closely related field in order to understand information technology principles. Equivalent work experience will be considered. Epic ex
P-1299 Databricks is radically simplifying the entire data lifecycle, from ingestion to generative AI and everything in-between. We’re doing it cross-cloud with a unified platform, currently serving over 10k customers, processing exabytes of data/day on 15+ million VMs, and growing exponentially. To
Samsung ElectronicsPosition Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center
NVIDIAA leading technology company in California is seeking an experienced engineer to join their CPU Cache Coherent Interconnects Design Team. You will work on the physical design of CPU interconnect networks and caches, engaging closely with the logic design team. A Master's degree and 5+ years of high-
ByteDanceA leading technology company in San Jose seeks a Research Engineer/Scientist for their Infrastructure team. This role involves designing and implementing distributed KV storage systems and optimizing caching for transformer-based models. Candidates should have a PhD in technical fields and robust ex
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architec
$40,000 – $63,000/year
Estimation confidence: Low
Estimate based on market data for Santa Clara. Actual salaries may vary depending on experience, company, and area.
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