Physical Design Implementation - 1,494+ job offers

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual

Apply now » Engineer Process Design & Implementation Posted Date: May 9, 2026 Requisition Number: 127547 Job Location: Hershey, PA Summary Reporting to the Senior Manager in the Process Engineering Group and working at the Technical Center in Hershey PA, the Process Engineer position will, with

Job Location: Hershey, PA Summary: Reporting to the Senior Manager in the Process Engineering Group and working at the Technical Center in Hershey PA, the Process Engineer position will, with direction, participate in the conceptual and detailed engineering design, execution, and implementation of l

Are you a dedicated technology professional passionate about technical design and project management? Are you a dynamic, solution-oriented leader seeking an inclusive, customer-centric atmosphere? Do you excel in collaborating with a diverse range of internal and external stakeholders, managing syst

ANZ

This is a Senior Consultant - Organisation Design and Implementation Senior Consultant - Organisation Design and Implementation role with ANZ based in Melbourne, VIC, AU == ANZ == Role Seniority - senior More about the Senior Consultant - Organisation Design and Implementation Senior Consultant - Or

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integr

7Rays Semiconductors

We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes. Key Responsibilities: Perform synthesis using Cadence Genus for large, timing-challenged designs Drive PPA (power, performance, area)

Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commerci

Implementation Design Lead I Are you a dedicated technology professional passionate about technical design and project management? Are you a dynamic, solution-oriented leader seeking an inclusive, customer-centric atmosphere? Do you excel in collaborating with a diverse range of internal and externa

Apex Systems

Job#: 3027134 Job Description: Physical Design Engineer - Wireless RF Silicon Location: San Diego, CA Type: Contract Role Overview The client is developing next-generation silicon to power a global Low Earth Orbit (LEO) satellite communications network. The Wireless RF Silicon team is seeking a Phys

Vertisystem Inc.

Role: Senior PKI Architect Design & Implementation Specialist Duration: 12+ Months (High possibilities of extension) Experience 10+ years of hands-on experience with Microsoft Active Directory Certificate Services (AD CS) -OR Equivalent platform, including design, deployment, and troubleshooting of

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's

Qualifications: Strong experience in RTL synthesis using Cadence Genus/Fusion compiler, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff con

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing fo

President at SBT | 19 years of advising leaders at semiconductor and deep tech companies | Architecting teams from startups to F500 organizationsCompany OverviewThis confidential client is strategically bringing on a Director of Physical Design Engineering to build and lead a PD organization from th

Who you are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration Strong problem solver who excels at debugging complex issues across desig

Comcast

Comcast brings together the best in media and technology. We drive innovation to create the world's best entertainment and online experiences. As a Fortune 50 leader, we set the pace in a variety of innovative and fascinating businesses and create career opportunities across a wide range of location

Company Overview At Motorola Solutions, we believe that everything starts with our people. We’re a global close-knit community, united by the relentless pursuit to help keep people safer everywhere. We build and connect technologies to help protect people, property and places. Our solutions foster t

Description Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. The Role Be part of Amazon Leo’s ASIC team responsible for defining and implement