78 rtl opportunities in San Francisco updated today
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· Page 1 / 4Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership o
About the job Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark , General Catalyst , Peter Thiel , Adam D'Angelo , Larry Summers , and Jack Dorsey . Position: RTL Design Engineers Type: Contract Compensa
What to Expect The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hard
4 Staffing CorpAbout the job Lead ASIC RTL Design Engineer Lead ASIC RTL Design Engineer - Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute plat
We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors. Employment Type: Full-Time Permanent Location: Redwoor City, CA (onsite) Work Status: Work authorization in t
A leading technology company in San Francisco is looking for a Cellular ASIC Design Engineer to architect and implement protocol processing hardware for wireless SoCs. The candidate should have over 10 years of relevant experience and strong skills in SystemVerilog and Verilog. Responsibilities incl
4 Staffing CorpLead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take o
Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership o
4 Staffing CorpAbout the job Lead ASIC RTL Design Engineer Lead ASIC RTL Design Engineer - Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute plat
A leading electric vehicle and energy company is seeking an ASIC RTL Design Engineer to contribute to custom ASIC development for AI systems. Located in California, you'll design and implement Ethernet IP integration, optimize SoC clocks, and collaborate with cross-functional teams. Candidates shoul
A leading AI organization in San Francisco is seeking an RTL Engineer to design components for their custom AI accelerator. Candidates should have experience in hardware-software co-design and a strong background in Verilog/SystemVerilog. This hands-on role offers the opportunity to work within a hy
Responsibilities To be considered for an interview, please make sure your application is full in line with the job specs as found below. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, incl
Responsibilities To be considered for an interview, please make sure your application is full in line with the job specs as found below. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, incl
Responsibilities To be considered for an interview, please make sure your application is full in line with the job specs as found below. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, incl
Responsibilities To be considered for an interview, please make sure your application is full in line with the job specs as found below. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, incl
Responsibilities To be considered for an interview, please make sure your application is full in line with the job specs as found below. Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design integration of the Ethernet IO subsystem, incl
In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. You will develop signal processing intensive design for wireless communication SoCs with diverse connectivity technolog
As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - de
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac We are looking for an experienced engineer to drive CPU machine-learning accelerator architecture and RTL development
Avlyn GroupWe are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors. Employment Type: Full-Time Permanent Location: Redwoor City, CA (onsite) Work Status: Work authorization in t
TalencoreWe are seeking a Sr. RTL Verification Engineer to join our client's team in Redwood City who is inspired to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors. Employment Type: Full-Time Permanent Location: Redwood City, CA (onsite) Work Status
Company Description TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware. We offer a very competitive compensation, commensu
Ricursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. We are hiring best
Job Title: RTL Design Engineer Location: Fremont , California, United States Duration: Full Time Role ROLES & RESPONSIBILITIES: Lead RTL design, simulation, and verification efforts for ASIC/SoC products, ensuring robust and efficient designs Integrate and validate IP blocks within the larger system
A global industrial software leader is seeking a seasoned professional to develop comprehensive verification IPs for advanced interfaces including PCIe and Ethernet. The role demands over 15 years of RTL design experience and expertise in SystemVerilog and UVM. Join a diverse team dedicated to innov
TeslaASIC RTL Design Engineer, AI Hardware Tesla The Tesla AI Hardware team is looking for a Senior ASIC RTL Design Engineer to work on industry-leading AI accelerators in Palo Alto, CA. The candidate is expected to implement and document microarchitecture specifications, define system‑level functional r
A leading tech company headquartered in Palo Alto is seeking a Senior ASIC RTL Design Engineer to work on state-of-the-art AI hardware. Ideal candidates should have a strong background in low power microarchitecture, Verilog RTL design, and extensive experience in the industry. This position will in
A leading AI accelerator company in San Bruno, California is seeking a Hardware Engineer to join their hardware team. In this role, you will design and implement RTL for a neural network accelerator, ensuring functional correctness through collaboration with hardware architects. The ideal candidate
$40,000 – $63,000/year
Estimation confidence: Low
Estimate based on market data for San Francisco. Actual salaries may vary depending on experience, company, and area.
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