Amogh Thakur
Design Verification Engineer
Talent
PortlandMember since September 29, 2026
SystemVerilogVerilogPythonUVMFunctional CoverageCocotbScan ChainPipeliningMemory HierarchyQuestaSimCadence GenusDFIUART
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SystemVerilogVerilogPythonUVMFunctional Coverage
About
Developed weekly stakeholder dashboards with Matplotlib and Pandas, surfacing KPI trends and troubleshooting anomalies across data sources on live production servers for 20+ cross-functional business stakeholders and demonstrating customer .
Experience
Associate Engineer at Metro GSC (2023-08 – 2025-05)
- Developed weekly stakeholder dashboards with Matplotlib and Pandas, surfacing KPI trends and troubleshooting anomalies across data sources on live production servers for 20+ cross-functional business stakeholders and demonstrating customer.
Hardware Intern at Matrix Robotics (2021-08 – 2021-10)
- Tested and validated IoT embedded systems UART communication protocol; performed hardware calibration, signal monitoring, and system-level debugging, and performed board-level testing of clock signals, data integrity, and clock jitter.
Education
M.S. in Electrical and Computer Engineering – Portland State University (2025-09 – 2027-06)
Bachelor of Engineering in Electronics and Telecommunication – Pune Institute of Computer and Technology (2020-06 – 2023-06)
Skills
Design Verification Engineer
