Purvin Talati
Design Verification Engineer
Talent
San Jose, Santa ClaraMember since February 7, 2023
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About
Pursuing Masters in Electrical Engineering from San Jose State University
Experience
Holding 4 years of work experience in Design Verification domain.
-Worked on various FPGAs/SoC design verification environment.
Education
-RTL design and synthesis
-UVM
-System Verilog
