Andrew Chen

Senior FPGA Engineer with 8 years of experience delivering high-performance FPGA and DSP solutions for radar, communications, sensing, and embedded defense systems in multidisciplinary hardware and software environments. Experienced in translating complex customer requirements into scalable FPGA architectures using Verilog and SystemVerilog across signal processing pipelines exceeding 80 Gbps and timing closure targets above 500 MHz. Strong background in Digital Signal Processing, FPGA-based acceleration, hardware-software integration, and system-level optimization involving PCIe, DDR4, AXI, and high-speed SERDES interfaces.

Delivered more than 12 FPGA platforms supporting radar processing, data acquisition, and communications workloads while reducing end-to-end latency below 3 ms across integrated systems. Proven ability to lead technical design reviews, contribute to customer-facing proposals and project estimates, identify architectural risks early, and collaborate closely with electronics, firmware, and software teams on production-ready FPGA implementations.

Senior FPGA Engineer at BAE Systems, Inc (2022-01 – Present)

• Architected FPGA-based DSP pipelines for radar and sensing applications processing more than 82 Gbps of aggregate streaming data across 5 integrated subsystems.
• Delivered timing closure above 520 MHz on 3 high-speed FPGA platforms using SystemVerilog and optimized constraint strategies for multi-clock architectures.
• Integrated PCIe Gen4, DDR4, and 25G Ethernet interfaces into FPGA systems supporting real-time communications and sensor processing workloads.
• Collaborated with 8 hardware and software engineers to develop embedded FPGA solutions with end-to-end processing latency below 2.8 ms.
• Developed fixed-point DSP modules including FFT, FIR filtering, and signal conditioning blocks supporting 14-bit and 16-bit acquisition pipelines.
• Led technical design reviews and contributed to 11 customer proposal activities involving architecture tradeoffs, resource estimation, and implementation feasibility.
• Identified and mitigated timing and bandwidth risks across 4 complex FPGA programs by restructuring AXI interconnect and memory arbitration architectures.
• Mentored 4 FPGA engineers on DSP implementation techniques, simulation methodologies, and hardware bring-up procedures for production deployments.

FPGA Design Engineer at Logicircuit, Inc (2019-07 – 2021-12)

• Implemented RTL modules for communications and sensing applications using Verilog across FPGA subsystems operating at frequencies up to 320 MHz.
• Developed simulation testbenches validating more than 170 DSP and control-path scenarios covering packet processing and streaming data integrity.
• Integrated AXI4, DDR3, and Gigabit Ethernet interfaces into FPGA platforms supporting sustained throughput above 28 Gbps.
• Collaborated with firmware engineers on embedded C/C++ integration for 6 FPGA-based evaluation and prototype systems.
• Performed FPGA bring-up and hardware debugging across 9 prototype boards using logic analyzers, embedded debug cores, and signal integrity measurements.
• Reduced DSP pipeline latency by 1.1 ms across 3 signal-processing modules through optimized buffering and arithmetic scheduling techniques.
• Supported customer-facing technical discussions and pre-contract feasibility analysis for 7 defense and communications development programs.

Bachelor's Science in Computer Engineering – Binghamton University (2013 – 2018)