Naveen Desai

 Reliable and resourceful VLSI Engineer with 20+ years of experience in ASIC flow development from RTL to GDSII.

 Experience in Synthesis, Physical Design and Timing Closure with 20nm, 14nm 10nm ,7nm ,5nm ,4nm and 3nm technologies.

 Was part of 18 successful tapeouts.

 Experience in various aspects of ASIC Implementation – Synthesis, STA, Formal Verification, CTS, Place and Route,

Timing Closure and ECO flows.

 Experience in estimating implementation cycle for Synthesis / STA / Physical Design activities.

 Experience in project planning and leading a team.

 Strong problem solving, leadership, debugging and analytical skills.

 Reliable and resourceful VLSI Engineer with 20+ years of experience in ASIC flow development from RTL to GDSII.

 Experience in Synthesis, Physical Design and Timing Closure with 20nm, 14nm 10nm ,7nm ,5nm ,4nm and 3nm technologies.

 Was part of 18 successful tapeouts.

 Experience in various aspects of ASIC Implementation – Synthesis, STA, Formal Verification, CTS, Place and Route,

Timing Closure and ECO flows.

 Experience in estimating implementation cycle for Synthesis / STA / Physical Design activities.

 Experience in project planning and leading a team.

 Strong problem solving, leadership, debugging and analytical skills.

Bachelor of Engineering in Electronics from Pune University, India, Year of Passing 1999.

P.G. Diploma in VLSI Design from Bit-Mapper Technology, Pune, India, NOV 2000.