Peter Michel
Digital hardware engineer specializing in FPGA-based real-time systems
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About
Digital hardware engineer specializing in FPGA-based real-time systems, with hands-on experience building pixel-pipeline VGA displays, fixed-point signal processing, and hardware-accelerated ML inference pipelines. Combines RTL design depth (SystemVerilog, Vivado/Vitis HLS) with strong software skills in Python and C. Comfortable across the full stack from register-transfer logic to application layer.
Experience
Firmware Engineer, Part Time at Medical Robotics and Computer Integrated Surgery Laboratory (2025-02 – 2025-05)
Collaborated with 2 engineers to develop an automatic verification system for MRI-compatible robotic catheter prototypes used in cardiac ablation surgery.
- Assisted in designing hardware files in KiCad for the various arduino and raspberry pi boards used to support the designed firmware for verification.
- Developed hardware to detect shorts within the catheter system, and then measure its inductive and resistive properties.
- Performed board level debug to assess and diagnose issues between the SPI communication of a raspberry pi chip and Direct Digital Synthesis chiplet.
- Refactored and debugged an existing monolithic codebase used to magnetically steer the catheter during use in an MRI via its inductors, solving critical ADC polling issues to achieve a consistent design.
Front End Web Development Intern, Full Time at SimCorp (2023-06 – 2023-08)
Worked in an international team, communicating in German and English.
- Led a project to create novel AI solutions to automate customer finance data tracking via a sentiment analysis model.
- Researched and selected optimal AI algorithms best suited for the project.
- Developed a user-facing Python/Flask app for tagging and rating sentiment of news articles, increasing training data throughput by 300%.
- Designed and implemented a reliable data transfer protocol (TCP/UDP) in Python featuring FSM-based connection management, RTT-based timeout estimation, and congestion-aware rate control. Used multithreaded send/receive pipelines with lock-based synchronization for shared state. Validated behavior under varied simulated network conditions in Linux.
Education
Master of Science in Electrical Engineering (Microelectronics) – RWTH Aachen (2025-10 – 2028-09)
Bachelor of Science in Computer Engineering – Case Western Reserve University (2021-08 – 2025-05)
