Suresh Gurappagari

Entry-level Physical Design Engineer with hands-on experience in RTL-to-GDSII flows using Synopsys tools (DC, ICC2, Fusion Compiler, Prime Time). Skilled in STA, timing closure, MMMC analysis, and physical verification (Calibre) through training and industry-relevant projects. Successfully implemented RISC-V and Router designs in 32nm technology.

Professional Training - Advanced VLSI Physical Design & Verification at Maven Silicon (2024-02 – Present)

• Implemented end-to-end RTL-to-GDSII flows on industry-standard Synopsys tools.
• Performed STA using PrimeTime, resolving violations and achieving timing closure.
• Applied DRC/LVS checks in Calibre to validate layouts before fabrication.
• Gained exposure to MMMC (Multi-Mode Multi-Corner) analysis ensuring design reliability across PVT corners.

B.Tech in Electronics & Communication Engineering – Sri Venkateswara Engineering College (2020 – 2024)

Intermediate in MPC – Sir CV Raman Junior College (2018 – 2020)