Thota Vamsi

Performance-driven firmware engineer with 4 years of production experience optimizing data center AI accelerators, automotive safety-critical systems, and mobile SoCs.

Proven ability to deliver measurable impact: 15–20% latency reductions, 10–12% power optimization, and sub-microsecond context-switch overhead. Expert in bare-metal drivers, microcode tuning, RTOS scheduling, and ISO 26262 functional safety. Shipped production firmware across Qualcomm, Bosch, and HCL; comfortable translating oscilloscope traces into merged pull requests.

Firmware Engineer - Qualcomm

(2025-12)

Data Center AI Accelerators & Mobile Flagship SoC Firmware

• Rewrote AI inference accelerator microcode scheduler to enable parallel execution pipelining; reduced end-to-end latency from 12.5 µs to 10.2 µs (18% improvement) on multi-billion-parameter production workloads, validated via performance counters.
• Redesigned HBM and DDR5 memory orchestration layer, eliminating allocation stalls through intelligent buffer pre-allocation and recycling; lifted sustained utilization from 65% to 80%+ under peak inference load.
• Rebuilt virtualization firmware context-switch path for multi-tenant inference hosting; maintained hardware switchover at 7–9 µs while preserving isolation guarantees, enabling higher consolidation ratios on serving platforms.
• Architected and deployed low-level NPU drivers for on-device generative AI inference, now active across 50M+ flagship devices (Snapdragon 8 Elite: Galaxy S25, OnePlus 13, Xiaomi 15) and cloud reference servers; improved local token-generation throughput by 20–25%.
• Implemented predictive dynamic clock-gating using workload history and custom power-state transitions; achieved 10–12% idle power reduction and extended thermal headroom by 15–20 minutes under sustained workloads (validated via power traces).

Firmware Engineer Intern - HCL Tech

(2025-02 - 2025-07)

Centralized Domain Controller & Software-Defined Vehicle (SDV) Platform Firmware

• Owned end-to-end OTA update pipeline validation on HIL rigs using Vector CANoe; reduced firmware flash time for 500 MB package over 5G gateway from 120s to 102s (15% reduction, 18-second savings per session).
• Enhanced battery management system (BMS) fast-charging sensor accuracy by 10% through rigorous validation of cell-voltage and thermal-monitoring drivers for safety-critical charge loops.
• Brought up SPI and Automotive Ethernet interfaces for ADAS and digital-key modules; held time-critical input latency under 2 ms to meet real-time requirements and validated on hardware in integration lab.
• Developed Python-based HIL test suites with Vector CANoe and logic analyzers; raised HAL driver test coverage above 30% and reduced manual validation time by 8 hours per build cycle.
• Resolved dozens of MISRA C/C++ violations and static-analysis findings; brought safety-critical codebase into full ISO 26262 functional-safety compliance.

Firmware Engineer - Bosch

(2021-06 - 2023-11)

Central Vehicle Computer & Zone ECU Firmware (Software-Defined Vehicle Architecture)

• Consolidated cluster, driver-monitoring, and infotainment data streams onto single SoC across Central Gateway, Cockpit Computer, and Chassis Controller (VW MEB, BMW iX, Mercedes platforms - 5M+ vehicles in production); reduced cross-domain routing latency by 15–20% while resolving multi-core synchronization race conditions.
• Implemented sensor-fusion microcode and low-level drivers for radar/camera arrays; held execution loops to sub-millisecond (0.8–1.2 ms) for automated emergency braking and lane-keeping systems - critical for ASIL-D safety integrity levels.
• Developed dual-core lockstep protection for steering and braking controllers through cross-comparing execution results; eliminated unscheduled hardware lockups with zero false negatives on injected fault testing, meeting ASIL-D functional-safety requirements.
• Built CAN-FD and Automotive Ethernet test automation across AUTOSAR Classic/Adaptive layers on Infineon processors using Lauterbach TRACE32 and CANoe; reduced test-case execution time by 30%.
• Cleared 40+ MISRA C/C++ violations and static-analysis findings; brought full software stack into ISO 26262 compliance for production release.

Embedded Software Intern - Bosch

(2020-12 - 2021-05)

Multi-Core MCAL Drivers for Central Gateway (CAN/LIN ↔ Automotive Ethernet Routing)

• Validated SPI, ADC, and CAN peripheral drivers on multi-core automotive MCU; optimized high-speed packet routing and reduced cross-bus latency by 10–12%.
• Integrated Hardware Security Module (HSM) cryptographic hooks into AUTOSAR Classic stack; verified frame authentication against microsecond-level timing budgets using EB Tresos and CANoe.
• Wrote Python and CAPL scripts for Software-in-the-Loop (SIL) testing; raised unit test coverage above 20% and caught register-level timing anomalies before hardware integration.
• Ran QAC static analysis and cleared compiler warnings; brought codebase to MISRA C compliance for ASIL-D targets.

M.S. - Information Technology Management - St. Francis College, New York, USA (2025-08)

B.Tech. - Electronics and Communication Engineering - Chalapathi Institute of Engineering and Technology, Andhra Pradesh, India (2022-05)