Valluru.m

Physical Design Engineer with extensive experience in end-to-end netlist-to-GDSII implementation at advanced technology nodes, including 5nm and 7nm, using Synopsys EDA tools. Proficient in block-level physical design for complex macros with up to 1.2 million gates, meeting power, performance, and area (PPA) targets. Skilled in floorplanning, placement, clock tree synthesis, routing, timing closure, parasitic extraction, power integrity, and physical verification.

Experienced in implementing engineering change orders (ECOs), optimizing PPA, and incorporating UPF-based low-power design strategies. Works closely with front-end teams to refine SDC constraints, improve design flows, and resolve implementation challenges in high-speed, high-density semiconductor designs.

PHYSICAL DESIGN ENGINEER at CISCO (2025-04 – Present)

• Performed end-to-end netlist-to-GDSII implementation of the 1.2-million-gate cr_rxai_fwd_macro block at 5nm using Synopsys Fusion Compiler and IC Compiler II, integrating 61 macros and targeting an operating frequency of 650 MHz.
• Developed the floorplan and power grid to optimize macro placement, minimize IR drop, and maintain routability in a high-density design.
• Worked closely with RTL, DFT, and integration teams throughout implementation and timing closure to support successful block integration and prepare the design for signoff.
• Performed static timing analysis using Synopsys PrimeTime and achieved positive slack on critical paths through targeted buffer insertion and cell sizing.
• Extracted parasitics using StarRC and back-annotated the results to enable accurate post-route timing and power analysis, supporting successful signoff.
• Refined the design flow to improve overall PPA, reducing dynamic power consumption by approximately 12% while meeting performance targets.
• Worked closely with front-end teams to refine SDC constraints and implement UPF-based low-power strategies to improve leakage power control.

PHYSICAL DESIGN ENGINEER at G SILICONTECH SOLUTIONS (2021-06 – 2023-07)

• Completed physical implementation of two 7nm blocks using Synopsys IC Compiler II: the 800K-gate Cr_rxai_acl_macro with 131 macros operating at 1 GHz and the 700K-gate Par_pcie4 with 42 macros operating at 0.8 GHz.
• Performed block-level floorplanning, power planning, and placement to manage congestion and maintain balanced utilization across the designs.
• Completed clock tree synthesis and routing, using PrimeTime to guide iterative timing optimizations and resolve setup and hold violations.
• Verified layouts using Synopsys IC Validator, ensuring they were DRC- and LVS-clean before tapeout.
• Analyzed IR drop and improved power integrity through targeted optimizations, adding decoupling capacitors where needed.
• Developed Tcl scripts to automate repetitive physical design tasks, streamline the flow, and reduce turnaround time.

Master of Science in Electronics & Electrical Engineering – University of New Haven

Bachelor of Technology in Electronics & Communication Engineering – Koneru Lakshmaiah Education Foundation