Ajith

VLSI Engineer with hands-on FPGA Prototyping and Pre-Silicon Validation experience from Synopsys HAPS-100/80 multi-FPGA platforms, including PCIe/USB protocol validation and RTL-to-bitstream bring-up. Currently at Phinity Labs evaluating and grading AI-agent-generated RTL for functional correctness and PPA efficiency. M Tech in VLSI Design; dissertation on Hardware Trojan Detection using unsupervised machine learning.

Design Engineer at Phinity Labs (Precursor Labs India Pvt Ltd) (2026-07 – Present)

• Reviewed and validated AI-agent-generated evaluation benchmarks on NVDLA RTL modules, making the calls on problem specs and grading criteria across functional correctness, area, and power variants for a single base module.
• Evaluated agent-suggested functional-correctness problems (RTL-generation and bugfix) against hidden cocotb test suites, confirming 100% functional coverage on RTL test designs in a WSL/Ubuntu environment using Icarus Verilog, cocotb, and cocotb-coverage.
• Reviewed PPA calibration runs — assessed agent-suggested optimization jobs, evaluated synthesized golden solutions extracted from agent runs, and made the call on ranking results into difficulty tiers for area (Yosys cell count) and power (OpenSTA dynamic power).
• Diagnosed a degenerate area-optimization axis versus a healthy power-optimization gradient across agent runs, and made the engineering call to scope the problem family accordingly rather than force an unsupported difficulty ladder.

FPGA Prototyping Intern at Intel Corporation (2025-07 – 2026-06)

• Execute the full RTL-to-bitstream flow to validate high-speed IP images on Synopsys HAPS platforms; optimized design partitioning and timing convergence to achieve high-performance bitstream generation.
• Owned bitstream deployment and system bring-up; validated protocol interfaces including PCIe and USB enumeration and link stability between target IPs and the host system.
• Built and executed validation test suites using Skyhawk and custom Python scripts to confirm functional parity of the IP image against design specifications.
• Partnered with the IP Design team to identify, debug, and root-cause hardware-level bugs found during real-time prototyping.
• Engineered Python and TCL scripts to automate the implementation flow, improving build reproducibility and operational efficiency.
• Used Verdi for deep-dive signal analysis and root-cause identification of hardware-software synchronization issues.

Mechatronics Engineer at Vesuvius India Ltd (2022-09 – 2024-06)

• Diagnosed and resolved failures in automated mechatronic systems, reducing production downtime
• Enhanced automation by integrating sensors and control systems while ensuring safety compliance.

M Tech in VLSI Design – Amrita Vishwa Vidyapeetham (2024-07 – 2026-05)

BE in Mechatronics – Acharya Institute of Technology (2018-09 – 2022-06)