Alwin Kurian
VLSI Verification Engineer (Trainee) with hands-on experience in SystemVerilog and UVM-based verification methodologies
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About
VLSI Verification Engineer (Trainee) with hands-on experience in SystemVerilog and UVM-based verification methodologies. Skilled in RTL design, testbench architecture, constrained random verification, functional coverage, assertions (SVA), and regression testing. Experienced in AMBA AXI/APB protocol verification and complete ASIC frontend flow including simulation, debugging, and verification closure using QuestaSim and VCS.
Experience
Trainee - Maven Silicon - Karnataka
(2025-06)
- Developed UVM-based verification environments including driver, monitor, sequencer, agent, and scoreboard components.
- Implemented constrained-random test scenarios and functional coverage models.
- Performed regression testing and debugged RTL failures using waveform analysis in QuestaSim.
- Verified AMBA AXI/APB protocol compliance through transaction-level stimulus generation and assertions.
- Worked on complete ASIC front-end flow including RTL design, simulation, debugging, and verification closure.
Education
B.Tech - Electronics & Communication Engineering - Mar Baselios Christian College of Engineering & Technology (2021-11 - 2025-05)
