Raveem Gouda
Design Verification Engineer with hands-on expertise in SystemVerilog, UVM, and AXI-based protocols
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About
Design Verification Engineer with hands-on expertise in SystemVerilog, UVM, and AXI-based protocols. Prior industry experience at AMD-Xilinx performing SoC-level system validation on Versal AI platforms. Proven ability to build self-checking, coverage-driven verification environments and debug complex protocol, phase, and regression issues. Strong HW/FW co-verification background from multi-core SoC bring-up and embedded validation work.
Experience
SoC Validation Intern at AMD – Xilinx (2022-12 – 2023-06)
- Performed SoC-level system validation on Versal AI platform — covering boot-flow, kernel, and user-space testing across QEMU emulation and real hardware bring-up.
- Executed HW/FW co-verification for the OpenAMP framework on multi-core SoC BSPs, validating inter-processor communication between Arm Cortex-A72 and RPU cores.
- Built Python-based regression test suites using pytest, Jenkins, and Xilinx-ROAST; automated validation reduced manual test time significantly.
- Strengthened practical knowledge of SoC architecture, processor asymmetric multiprocessing, and system-level behavior during platform bring-up.
Software Engineer at Capgemini Technology Services (2016-10 – 2019-07)
- Worked on SAP system monitoring, incident analysis, and automation for enterprise platforms.
- Automated alerts and reports using scripting, improving operational response time.
- Gained experience in large-scale system debugging and production issue handling.
Education
M.Tech in Embedded Systems & VLSI – NIELIT Calicut
