Arun Vaishnav

Design Verification Engineer with 2+ years of IC/SoC verification experience across complex protocol and memory subsystems, plus 2.5+ years in software engineering. Strong background in core skills like SystemVerilog, UVM, SVA, AXI, PCIe, python, VCS, and Verdi, with a track record of driving functional and code coverage closure on IP blocks within a high-performance computing SoC. Familiarity with AMBA (AXI/AHB/APB) and PCIe protocol verification, directly applicable to interconnect and NOC-based fabric work.

Proficient in Python automation for debug acceleration and reusable verification infrastructure.

Design Verification Engineer - Wipro Limited - Hyderabad, Telangana

(2024-07)

Project: Corsair - Intel's high-performance computing (HPC) chip with CSA (Configurable Spatial Accelerator) architecture. Client: Intel

• Developed and maintained modular UVM scoreboard, drivers, monitors, sequence, and coverage collector for 2 different memory operation engine IP blocks and SoC level with formal checkers for protocol graph execution verification. Leveraged GitHub Copilot (using Claude models) in VS Code to accelerate development.
• Developed and deployed SystemVerilog Assertions (SVA) for diverse interface protocols by translating design specifications directly from Hardware Architectural Specifications (HAS).
• Python Automation & Analysis: Engineered Python-based automation scripts to extract packet-level data from logs and implemented a custom AXI Protocol Tracker/Checker, reducing manual debug time and ensuring strict protocol compliance.
• Improved the memory operation tracker algorithm, improving performance by reducing time complexity from O(n²) to O(n), which cut execution time from 18 minutes to 8.5 minutes in large test environments.
• Debug & Coverage Closure: Utilized Synopsys Verdi for deep-dive waveform analysis to root cause critical RTL and test-bench bugs, directly contributing to improved simulation stability and faster functional coverage closure ensuring all debug artifacts were structured, well-tagged, and reusable across IP teams. Found more than 35 bugs including a critical bug in pipeline execution which improved system performance by a large margin and a cache Incoherency bug in architecture. Achieved over 97% f
• Verification Planning: Translated complex design specifications into structured test plans and coverage models, ensuring exhaustive metric-driven verification of corner cases and design features ensuring artifacts were contextualized and consumable for downstream automation and AI systems.

System Engineer - Tata Consultancy Services - Ahmedabad, Gujarat

(2022-02 - 2024-07)

Client: Cardinal Health

• Python: Developed and deployed python based data analysis tools for business process optimization.

B.E. - Electrical and Electronics Engineering - MBM Government Engineering College (2017 - 2021)