Bilwa Ghisad

• Currently working on Havasu Architecture in ASIC design 45nm PDK and used Nan-gate Open Cell library for virtuoso • Synthesized Verilog files for top module, programmable FSM, access control and generated reports for area, gates, timing, power • Performed Place and Route on access control with 8391.72um sq. as virtuoso core area and basic 4-bit adder modules, generated gds files using standard cells and imported them in virtuoso

Arizona State University, Computer Architecture and Embedded Systems Lab, Tempe, AZ January 2023 - Present

Graduate Service Assistant - Researcher (20 hours/week)

• Currently working on Havasu Architecture in ASIC design 45nm PDK and used Nan-gate Open Cell library for virtuoso • Synthesized Verilog files for top module, programmable FSM, access control and generated reports for area, gates, timing, power • Performed Place and Route on access control with 8391.72um sq. as virtuoso core area and basic 4-bit adder modules, generated gds files using standard cells and imported them in virtuoso

Master of Science in Computer Engineering (Electrical Engineering)

Graduating May 2023

Arizona State University, Tempe, AZ

GPA: 3.18/4.00

B.E. in Electronics and Telecommunication

June 2016 - May 2020

G. H. Raisoni College of Engineering (GHRCE), Nagpur, Maharashtra

GPA: 9.37/10.00

Relevant Coursework: VLSI Design, Constructionist Approach to Microprocessor Design, Digital Systems and Circuits, Computer Architecture II, Analog Integrated Circuits, Foundations of Algorithms, Python for Rapid Engineering Solutions