Chandu B V
Electronics Engineering student with hands-on knowledge in SystemVerilog, UVM, and protocols
Talent
BengaluruMember since May 30, 2026
VerilogSystem VerilogUVMFunctional CoverageAssertions (SVA)APBFSMFIFO DesignSynopsys VCSVerdi
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VerilogSystem VerilogUVMFunctional CoverageAssertions (SVA)
About
Electronics Engineering student with hands-on knowledge in SystemVerilog, UVM, and protocols. Skilled in testbench development, functional coverage, assertions, and debugging using Synopsys VCS. Seeking an entry-level role in VLSI Design Verification to apply verification methodologies and contribute to chip design.
Education
Bachelor of Engineering in Electronics and Telecommunication – Dr. Ambedkar Institute of Technology (2022-12)
12th Grade in PCMB – Jawahar Navodaya Vidyalaya (2020-01)
Skills
UVMand protocols
