Divya Kandipilli

Detail-oriented Analog Layout Engineer with 8 months of hands-on internship experience at MosChip Technologies in 28nm CMOS technology and 4 months of specialized Analog Layout training at MAST in 45nm CMOS technology. Experienced in custom analog and mixed-signal layout implementation using Cadence Virtuoso L and XL, with physical verification experience using Calibre DRC/LVS and Pegasus. Hands-on experience with Clock Generator Delay, PLL, Bandgap/Bias, and Resistor Calibration blocks in 28nm technology, along with Standard Cells, Op-Amp, Bandgap, DAC, and PLL blocks in 45nm technology.

Strong understanding of analog layout methodologies including floorplanning, device placement, routing, device matching, common-centroid, interdigitation, symmetry, dummy devices, guard rings, shielding, substrate noise reduction, latch-up prevention, antenna effects, PVT matching, EM/IR effects, and layout-dependent effects.

Analog Layout Intern - MosChip Technologies

Worked on custom analog and mixed-signal layout implementation using 28nm CMOS technology.

• Worked on Receiver blocks, gaining practical exposure to high-speed mixed-signal layout requirements.
• Worked on PLL, Bandgap/Bias, and Resistor Calibration, clk generator blocks.
• Performed block-level floorplanning, device placement, routing, and layout optimization.
• Used Cadence Virtuoso XL for custom analog and mixed-signal layout implementation.
• Applied placement strategies based on device matching, symmetry, noise sensitivity, signal integrity, and parasitic considerations.
• Implemented common-centroid structures for matched devices where required.
• Applied interdigitation techniques to improve matching and reduce systematic mismatch.
• Used dummy devices to improve edge-effect uniformity and matching performance.
• Implemented guard rings for substrate isolation, latch-up prevention, and noise reduction.
• Applied shielding techniques around sensitive analog and high-speed nets to minimize unwanted coupling and noise.
• Performed routing considering parasitic resistance, capacitance, coupling, congestion, and critical signal paths.
• Performed physical verification using Calibre DRC/LVS and Pegasus.
• Debugged and resolved DRC violations, LVS mismatches, connectivity issues, and layout-related errors.
• Checked layout connectivity against schematic requirements during LVS debugging.
• Considered PVT matching, WPE, STI, LOD, EM, IR-drop, antenna, and ESD effects during layout implementation.
• Participated in the layout verification debugging optimization cycle.
• Followed technology-specific design rules and analog layout guidelines during implementation.

Analog Layout Trainee - MAST

Completed 4 months of hands-on Analog Layout training using 45nm CMOS technology.

• Developed practical knowledge of custom analog and mixed-signal layout methodologies.
• Worked on Standard Cells, Operational Amplifier, Bandgap, DAC, and PLL blocks.
• Performed floorplanning, device placement, routing, and layout optimization.
• Practiced common-centroid, interdigitation, symmetry, and dummy-device techniques.
• Implemented guard rings for substrate isolation and latch-up prevention.
• Practiced shielding techniques for sensitive analog signals.
• Developed understanding of PMOS/NMOS placement, wells, substrate connections, taps, and guard structures.
• Gained exposure to DRC, LVS, and ERC verification concepts.
• Studied antenna effects and antenna prevention techniques.
• Developed understanding of WPE, STI, LOD, EM, IR-drop, ESD, and PVT matching considerations.
• Practiced layout techniques for reducing mismatch, coupling, substrate noise, and parasitic effects.

Bachelor of Technology - Electronics & Communication Engineering - Aditya College of Engineering (2024)

Intermediate - Sri Chaitanya Junior College (2020)

SSC - Little Buds Public School (2018)