Rohith Tm

Hiii...👋

Myself Rohith, EEE'25 batch from GCT Coimbatore.

I'm an Analog Layout intern at Texas Instruments, working on TSMC 28nm technology, and I am responsible for block-level floorplanning, routing, DRC/LVS verification, and PEX extraction for circuits such as LDOs, current mirrors, and operational amplifiers.

Started my career as an Analog Layout Intern at Texas Instruments, Bangalore.

• Worked on analog layout in TSMC 28nm process using Cadence Virtuoso Layout XL.
• Handled block-level floorplanning, routing, DRC/LVS verification and PEX extraction for IP blocks.
• Familiar with layout-dependent effects and CMOS fabrication process.
• Implemented matching techniques (common-centroid, inter-digitized, symmetrical).
• Optimized layouts for parasitic reduction, shielding, RC delay, EM, coupling, latch-up.
• Designed layouts for differential pairs, LDO, op-amps, current mirrors.
• Automated basic tasks using SKILL scripting to complete layouts efficiently.

BE Electrical and Electronics Engineering with minor degree in VLSI Design,

Government College of Technology, Coimbatore