Konda Shivateja

Aspiring VLSI Engineer with practical experience in the complete RTL-to-GDSII flow, specializing in block-level physical design implementation. I have successfully delivered tape-out ready designs, including the 'Iguana SOC' (300K gate count), by executing synthesis, floor planning, placement, and routing while resolving complex DRC and timing violations. Proficient in industry-standard tools such as Cadence Innovus, Genus, and Tempus, I utilize TCL and Python scripting to automate workflows and enhance design reliability.

I am actively seeking a Physical Design or ASIC Engineering role to contribute to high-performance hardware innovations.

My expertise in Physical Design is anchored by the successful execution of complete RTL-to-GDSII flows for complex block-level implementations. I led the backend implementation of the "Iguana SOC," a design featuring a 300K gate count and 32 integrated macros, where I managed floor planning, placement, Clock Tree Synthesis (CTS), and routing. To enhance flow efficiency, I developed automated scripts to detect and remove floating wires and shorts, while meticulously resolving setup and hold timing violations to deliver a tape-out ready GDSII.

Similarly, for the "RP_TOP" project, I automated the synthesis and physical design for a 50K gate-count block, focusing on congestion reduction and clearing all Design Rule Check (DRC) violations to ensure high manufacturability and design closure.

Beyond physical implementation, I have driven innovation in SoC architecture and circuit design through research-intensive projects. I designed "CHIPSETRON," a custom IoT SoC that integrates a proprietary high-performance processor core with peripherals onto a single VLSI chip to minimize latency and power consumption. My work in memory architecture includes developing a 10T SRAM-based In-Memory Computing design using TSMC 28nm technology, which successfully performed logic operations directly within the memory array using Cadence Virtuoso.

Additionally, I demonstrated proficiency in hardware-software co-design by implementing a real-time GNSS receiver on a Zynq SoC, leveraging FPGA fabric for signal acquisition and ARM cores for navigation computation

Final Year student at VNR Vignana Jyothi Institute of Engineering & Technology