Kusshal
Aspiring VLSI Design Verification Engineer
Talent
Bangalore, New South WalesMember since August 18, 2026
VerilogSystemVerilogUVMPythonScikit-learnVivadoVCSQuestaSimRandom ForestSVMNaive BayesStreamlit
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VerilogSystemVerilogUVMPythonScikit-learn
About
Aspiring VLSI Design Verification Engineer with hands-on experience in Verilog, SystemVerilog, UVM, and Python. Passionate about ASIC/FPGA verification, automation, and AI-assisted verification workflows.
Experience
Advanced VLSI Design and Verification Trainee - Maven Silicon Softech Pvt. Ltd.
(2025-09 - 2026-06)
- Developed expertise in Verilog, SystemVerilog, and UVM-based verification.
- Built functional testbenches, debugged simulations, and applied industry-standard verification methodologies.
PCB Manufacturing Intern - RIKUN Manufacturing Pvt Ltd
- Assisted in PCB fabrication and assembly processes.
- Inspected boards for manufacturing defects and quality compliance.
- Worked with Gerber files, drill files, and PCB production documentation.
- Learned PCB manufacturing workflow, soldering, testing, and quality control procedures.
Education
B.Tech - Electronics and Communication Engineering - Vellore Institute of Technology, Chennai (2021 - 2025)
Higher Secondary Education - Vels Vidyashram CBSE School (2021)
Skills
Aspiring VLSI Design Verification Engineer
