Yash Satone

Motivated and detail-oriented aspiring VLSI Design Verification Engineer with a solid foundation in SystemVerilog (SV), UVM methodology, and SystemVerilog Assertions (SVA), along with strong debugging skills and core verification concepts. Passionate about solving complex silicon challenges and seeking an entry-level role in a forward-thinking semiconductor organization to grow through hands-on project experience.

Advanced VLSI Design Verification Intern (2026-05 – 2026-08)

• Completed industry-oriented training in digital design and functional verification methodologies.
• Learned SystemVerilog (SV), UVM methodology, and the APB protocol, along with Verilog, FSM/FIFO design, and RISC architecture.
• Gained exposure to TCL scripting, Linux, and the ASIC design flow used in industry verification environments.

B.Tech in Electronics and Telecommunication Engineering – Bapurao Deshmukh College of Engineering, Sevagram (2021 – 2025)

Class XII – GBMM High School, Hinganghat (2019 – 2021)