Monish

Electronics and Communication Engineering graduate with hands-on training in ASIC Physical Design at 28nm technology. Skilled in RTL-to-GDSII implementation, including Floorplanning, Placement, CTS, Routing, Static Timing Analysis, Timing Closure, Physical Verification, and Signoff using Synopsys tools. Seeking to contribute as a Physical Design Engineer in a backend VLSI design team.

VLSI Physical Design Trainee - VLSIGURU - Bangalore

(2025-08 - 2026-03)

• Completed a full RTL-to-GDSII implementation flow for 28nm ASIC designs.
• Performed Floorplanning, Placement, Clock Tree Synthesis, Routing, and timing optimization.
• Achieved timing closure in PrimeTime by resolving setup and hold violations.
• Resolved DRC and LVS violations to generate signoff-ready GDSII.

B.E. - Electronics and Communication Engineering - Government College of Engineering, Erode (2021 - 2025)

Higher Secondary Certificate (HSC) - Wisdom Matriculation Higher Secondary School