Pathro Narendra

VLSI Physical Design Engineer with hands-on experience in 28nm RTL-to-GDSII ASIC implementation flow using Synopsys and Cadence tools. Skilled in synthesis, floorplanning, placement, CTS, routing, congestion optimization, and timing closure. Familiar with sign-off methodologies, physical verification flows, and PPA optimization techniques. Passionate about contributing to high-performance semiconductor designs and advanced physical design methodologies.

Physical Design Training - SEAGI - Tirupathi

(2024)

Completed intensive training in Physical Design with hands-on exposure to full RTL-to-GDSII flow at 28nm technology

• Experience in synthesis, floorplanning, placement, CTS, routing, ECO, congestion reduction, and timing optimization
• Familiar with sign-off verification flows including DRC, LVS, antenna checks, and timing analysis methodologies
• Hands-on exposure to Synopsys Design Compiler (DC), ICC2, Cadence Genus, and Innovus
• Strong understanding of ASIC implementation methodologies and physical design automation using TCL scripting

Bachelor of Technology (BTech) - Electronics & Communication Engineering - SEAGI (Affiliated to JNTU-A) (2024)

Intermediate - MPC - SR Junior College (2020)

SSC - Zilla Parishad High School (2018)