Naveen C

A motivated VLSI design engineer with an internship experience at GE Healthcare, specializing in Verilog and SystemVerilog for RTL coding and verification. Proficient in industry-standard EDA tools such as Xilinx Vivado, Cadence Virtuoso, and ModelSim, with strong skills in synthesis and simulation. Eager to contribute to innovative semiconductor projects and advance professionally within the industry.

• Participated in the RTL design and verification of an incremental encoder interface, and uart interface, including handling clock domain crossing (CDC) to ensure reliable data transfer between different clock domains. 
•  Worked with industry-standard EDA tools such as Xilinx Vivado, Quartus Prime, and Modelsim. 
•  Executed dysfunction test cases to verify the successful execution of the RSU for the Cyclone V FPGA. 
•  Contributed to the New Product Introduction (NPI) project, focusing on testing and verifying the Central Processing Unit (CPU) base board for a mammography machine using established test procedures.

Completed MTech in VLSI design from Amrita vishwa vidyapeetham from Bangalore with overall CGPA of 8.29.