Raj Deepak Singh
FPGA Design Engineer – RTL Design & Verification
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About
M.Tech VLSI student at NIT Raipur with hands-on experience in FPGA-based RTL design and verification using Verilog, SystemVerilog, and Xilinx Vivado. Skilled in designing and verifying digital systems including processors, memory controllers, and bus protocols, with strong fundamentals in UVM, SystemVerilog Assertions (SVA), and timing-aware RTL development. Passionate about translating system-level architecture into synthesizable, FPGA-deployable RTL.
Experience
Design & Verification Intern - Semi Design - Semiconductor Manufacturing
(2025-05 - 2025-07)
- Built and validated UART RTL and FIFO modules using Verilog and SystemVerilog with UVM-based functional verification.
- Developed SystemVerilog Assertions (SVA) and constrained-random tests to validate protocol corner cases.
- Investigated RTL and verification issues using assertions and waveform-driven debug techniques.
Design & Verification Trainee - VLSI Guru Ji Institute
(2026-01)
- Executing functional verification for high-speed AMBA AHB/AXI protocols and peripheral logic.
- Developing test plans and coverage models to ensure robust, timing-aware RTL validation.
Education
M.Tech - VLSI and Embedded Systems - National Institute of Technology (NIT) Raipur (2024-08 - 2026-06)
B.Tech - Electrical and Electronics Engineering - G.L.
Bajaj
Institute of Technology and Management (2014-08 - 2018-06)
Senior Secondary - Class XII - Saraswati Shishu Mandir Sr. Sec. School (2012-06 - 2013-06)
