Inder Jeeth Kaur
VLSI Physical Verification Engineer
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About
Detail-oriented and passionate VLSI Physical Verification Engineer with 3 years of hands-on experience in advanced semiconductor design verification at 5nm and 7nm technology nodes. Proficient in DRC, LVS, ERC, and IR drop analysis, with a strong command of Mentor Calibre, Synopsys IC Validator, and Tcl/Perl scripting for automation. Proven track record of delivering signoff-quality designs, resolving complex physical verification issues, and collaborating effectively with cross-functional teams.
Eager to contribute to cutting-edge chip designs and high-performance SoC projects.
Experience
VLSI Physical Verification Engineer at Capgemini Technology Services (2022-10 – 2025-09)
- Executed full-chip and block-level physical verification (DRC, LVS, ERC) for high-complexity SoC designs.
- Resolved critical issues including antenna violations, RV issues, SIGEM violations, and IR drop violations.
- Used Tcl-based automation scripts, reducing manual effort and improving verification turnaround time.
- Collaborated with RTL, PD, and layout teams to ensure clean signoff and tapeout readiness.
Education
Bachelor of Technology (B.Tech) in Electronics and Communication Engineering – Stanley College of Engineering and Technology for Women (2021-07)
