Prateek Sharma
RTL Design and Verification Engineer
Hire this person
Send a job offer directly to this candidate
About
RTL Design and Verification Engineer with a strong foundation in digital design principles, Finite State Machines (FSMs), and SystemVerilog. Experienced in using industry-standard EDA tools, including Xilinx Vivado and QuestaSim, for simulation, debugging, and functional verification. Skilled in building self-checking testbenches.
Eager to apply knowledge of constrained-random verification, assertion-based verification (SVA), and Universal Verification Methodology (UVM) to deliver reliable, high-performance digital circuits.
Experience
Project Intern - ISRO – ISTRAC - Bengaluru, Karnataka, India
(2026-06-15 - 2026-07-24)
Project: Design and FPGA Implementation of PM Modulator
- Designed and implemented a Phase Modulation (PM) Modulator using Verilog HDL for FPGA-based communication systems.
- Developed RTL modules and verified functionality through simulation using Xilinx Vivado.
Education
Bachelor of Technology - Electronics and Communication Engineering (ECE) - SRM University Sonepat (2027)
Higher Secondary Certificate - Class XII, CBSE - School of Excellence Rohini Sector 23 (2022)
Secondary School Certificate - Class X, CBSE - Govt. Co-ed Sarvodaya Vidyalaya Rohini Sector 21 (2020)
