S Lavanya

Results-driven RTL Design and Verification Engineer with extensive hands-on experience in Verilog, SystemVerilog, and UVM-based verification. Proficient in assertion-based verification and functional coverage, dedicated to delivering high-quality verification of digital designs. Committed to leveraging industry-standard methodologies and tools to enhance design integrity and performance. Passionate about driving innovation and excellence in complex digital systems.

Graduate Trainee Engineer at RV-VLSI Design Center (2025-07 – Present)

Engaged in RTL design and verification projects focusing on protocol verification and UVM testbench development.

• Developed UVM testbench to verify read/write operations
• Verified protocol compliance including SETUP and ACCESS phases
• Created test-cases for wait states and error responses
• Developed TX/RX agents for packet-level verification, verified packets using SOP/EOP
• Developed constrained-random stimulus for varied payload conditions
• Verified burst transactions (INCR, WRAP) and pipeline behavior
• Verified corner cases with constrained-random stimulus
• Achieved functional coverage of 72% and improved through targeted tests

Advance Diploma in ASIC Design: RTL Design And Verification – RV-VLSI Design Center (2026-01)

B.Tech in Electronics and Communication Engineering – Bharath Institute of Higher Education And Research (2025-04)