Analog, IO, ESD Layout design engineer
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Hi,
I am experienced professional in analog layout domain, I worked in Globalfoundries, Bangalore.
I have experience from 7nm to 350nm technodes.
14+ years of experience in IO/Analog layout design domain. Responsible for delivering GPIO, DDR, LVDS, ESD cells, PLL, ADC, DAC, special purpose IO, support cells with mini test chip verification. Worked from 7nm to 350nm technologies for various foundries including GlobalFoundries, TI, TSMC, Samsung, Fujitsu. Hands on experience in delivering from LEF to final gds with high quality layout design. Expert in solving complex layout design related issue
14+ years of experience in IO/Analog layout design domain. Responsible for delivering GPIO, DDR, LVDS, ESD cells, PLL, ADC, DAC, special purpose IO, support cells with mini test chip verification. Worked from 7nm to 350nm technologies for various foundries including GlobalFoundries, TI, TSMC, Samsung, Fujitsu. Hands on experience in delivering from LEF to final gds with high quality layout design. Expert in solving complex layout design related issue
