Swapnil Anand
VLSI Engineer
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About
Working on advanced technology nodes (18A,20A) for Intel's std cell library development.
Experience
VLSI Engineer - WIPRO
(2025-05)
Working on advanced technology nodes (18A,20A) for Intel's std cell library development.
- Characterized various Std. Cells libraries, covering timing, power, noise and LVF across multiple PVT Corners.
- Executed characterization & Quality validation of .lib models meets performance specs.
- Debug Characterization issue, striving appropriate solutions, and sign-off accuracy.
- Handled full Library release and post-release QA.
Hardware Design Engineer - Puncham Semicon Pvt. Ltd.
(2024-08 - 2025-04)
Client: Qualcomm
- Characterization of Standard Cell Libraries (TSMC 2nm, 3nm Nodes).
- Quality Checks on timing models (AOCV, LVF) to meet performance specs.
- Executed QA of Liberty and Verilog models including Cell List consistency, Lib vs LEF/Netlist, Structure Checks.
- Handled full Library release and post-release QA.
Design Engineer - Puncham Semicon Pvt. Ltd.
(2023-08 - 2024-07)
Characterization of Std cell libraries (TSMC 16nm, 28nm, GlobalFoundries 180nm, 90nm Nodes). Schematic, Simulation, and Characterization of circuit design processes, ensuring efficient library generation, validation, & across multiple PVT corners, including NLDM, CCS, CCSP, CCSN models for timing, power, and signal integrity analysis.
Assistant Network Engineer - SITI Broadband Pvt Ltd.
(2016-02 - 2018-02)
My role was to provide quality services in NOC operations.
- Implementation, Maintainence and Regulation of Cisco network device health and troubleshooting
Education
M. Tech - Microelectronics - Indian Institute of Information Technology, Allahabad (2021 - 2023)
B.Tech - Electrical and Electronics Engineering - KIIT University, Bhubaneshwar (2012 - 2016)
