Varun S L

VLSI Design Verification professional with hands-on experience in Verilog, SystemVerilog, and UVM. Experienced in developing UVM-based verification environments, testbenches, assertions, functional coverage, and protocol verification. Developed an AXI3 VIP and an APB-based SPI controller with experience in simulation, waveform analysis, debugging, and verification using QuestaSim, VCS, and Vivado. Seeking an entry-level Design Verification Engineer role.

VLSI Trainee at Maven Silicon (2025-09 – Present)

• Acquired strong fundamentals in digital design, Verilog, SystemVerilog, and UVM, with hands-on exposure to RTL design and verification concepts.
• Gained practical experience in simulation, debugging, and protocol-based design using industry tools such as QuestaSim, VCS, and Vivado.

B.E in Electronics and Communication Engineering – JSS Science and Technology University, Mysore (2025-08)

Diploma in Electronics and Communication Engineering – Government Polytechnic, Soraba (2022-06)