Vivek Havalad

Fresher Design Verification Engineer with hands-on project experience in SystemVerilog and UVM, skilled in building reusable, coverage-driven testbenches and verifying industry-standard protocols like AXI. Seeking an entry-level DV role to apply strong fundamentals in constrained-random verification, functional coverage, and assertion-based checking.

B.E. in Electrical and Electronics Engineering – University Visvesvaraya College of Engineering, Bengaluru (2021 – 2025)

12th – Bendre PU College (2019 – 2021)

10th – Jawahar Navodaya Vidyalaya (2019)