Himanshi Dalmia

VLSI Physical Design | RTL Design | FPGA Development

Talent

NoidaMember since August 19, 2026

Verilog HDLCadence GenusCadence InnovusRTL SynthesisFloorplanningPlacementCTSRoutingSTATiming ClosureXilinx VivadoUARTSPII²CFSM DesignTiming Analysis

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Verilog HDLCadence GenusCadence InnovusRTL SynthesisFloorplanning

About

B.Tech Electronics & Communication Engineering student (CGPA 9.25/10) with hands-on experience in ASIC Physical Design, RTL Design, and FPGA Development. Currently pursuing a 12-week Physical Design Internship at NIT Delhi, working on Cadence Genus and Innovus across the RTL-to-GDSII flow. Experienced in Verilog HDL, Vivado, timing analysis, FPGA prototyping, and digital system design. Seeking opportunities in Physical Design, RTL Design, FPGA, and ASIC Design Engineering.

Experience

Research Intern - NIT Delhi - Delhi

(2026-05 - 2026-07)

Gaining hands-on experience in the complete ASIC RTL-to-GDSII Physical Design flow using Cadence Genus and Cadence Innovus.
Performing RTL synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), routing, and Static Timing Analysis (STA) for digital designs.
Analyzing timing, area, and power reports while learning timing closure and physical design optimization techniques.

Student Intern - BITS PIEDS, Pilani - Pilani

(2025-06 - 2025-07)

Completed a 2-month internship focused on embedded systems, gaining hands-on experience in PCB designing, 3D modelling, and embedded hardware development.
Worked on system integration and basic debugging, developing practical understanding of hardware-oriented design workflows.

Project Lead - IEEE BKBIET SB - Pilani

(2024-10)

Planned and led hands-on workshops on Embedded Systems and IoT, delivering technical sessions on microcontrollers, sensors, and system-level design.
Mentored students during practical sessions and guided juniors in digital electronics and embedded fundamentals.