Javeria

Electrical Engineering graduate from UET Lahore with hands-on experience in RISC-V vector processor design, hardware verification, and optimization, and a strong interest in SystemVerilog, digital system design, computer architecture and layer testing verification.

Hardware Design & Verification Intern at Xcelerium Pvt. Ltd. (2025-08 – Present)

• Worked on digital hardware design and verification using SystemVerilog and worked on various C programming tasks.
• Studied and implemented hardware including UART, AXI, SPI and FIFO buffers, cache and memory integration and optimization, bus arbiters, bus integration with modules, Finite state machines, counters.
• Implemented layer testing environment for some combinational and sequential modules.
• Built a verification setup to test, validate, and troubleshoot hardware modules, identifying and resolving functional bugs.
• Documented test procedures and results and contributed to multiple concurrent hardware projects.

Hardware Design Trainee at Maktab-e-Digital Research Lab (2025-06 – 2025-08)

• Completed structured technical training focused on digital hardware design fundamentals and tool proficiency.

Bachelor of Science in Electrical Engineering – University of Engineering and Technology Lahore (2022 – 2026)

FSc in pre-Engineering – Govt Islamia College for women cooper road Lahore (2015 – 2020)

Matriculation – Queen Mary College Lahore (2015 – 2020)