85 sta opportunities in San Jose updated today
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· Page 1 / 5STA / Timing Implementation Engineer (PCIe Focus) Role Overview We are seeking a Timing Implementation Engineer with strong expertise in Static Timing Analysis (STA) and constraint development for high-speed interfaces such as PCIe. This role is focused on implementation and timing closure , not des
Efficient ComputerEfficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML fr
The application window is expected to close on: 04/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provid
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold id
What to Expect The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technol
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what
Job Details: Job Description: We are seeking an experienced Senior Static Timing Analysis (STA) Developer to architect, design, and optimize next-generation timing analysis engines for advanced ASIC and FPGA design flows. This role is ideal for someone who has deep expertise in STA algorithms, large
THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold id
Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML fr
Quest Global ManufacturingJob Requirements What will you do : Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies; preferable in-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesi
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology. - Work with design teams to understand and debug constraints and facilitate logic changes to imp
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. - Work with design teams to understand and debug constraints and facilitate logic changes to imp
Overview Location: San Jose Team: Facilities Employment Type: Regular Job Code: A145407A Responsibilities Support the TM team in managing the full-cycle transaction process, from initial business case development and site selection to supporting the decision-making process and the final execution of
Role Summary We are seeking a proactive Real Estate Transaction Management Analyst to support our AMS Transaction Management (TM) team. In this role, you will be at the heart of our real estate strategy, assisting in the execution of lease transactions and portfolio management. You will collaborate
Role Number: 200605480-3749 Summary Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working peo
A leading AI technology company is looking for a Staff Design for Test STA Engineer. You will ensure the testability and performance of next-generation AI processors. The ideal candidate has deep knowledge of DFT concepts and experience in Static Timing Analysis for complex SoCs. This hybrid role is
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integr
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
Cupertino, California, United States Hardware Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people
*STA Engineer** *Bay Area, CA – onsite** *Contract** *KEY RESPONSIBILITIES:** Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater plan
*Company Description** We suggest you enter details here. *Role Description** This is a full-time, on-site role for a Senior Physical Design Engineer/STA located in California, United States. The Senior Physical Design Engineer will be responsible for end-to-end implementation of physical design pro
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
*Company Description** Saika Technologies, Inc. is a forward-thinking technology solutions company committed to pushing the boundaries of innovation in the semiconductor domain. Located in the heart of the San Francisco Bay Area, Saika Technologies partners with leading companies to create cutting-e
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
Mirafra TechnologiesKey Responsibilities: Perform Static Timing Analysis (STA) for ASIC/SoC designs Handle timing closure across multiple corners and modes Work on timing sign-off using industry tools Analyze and debug timing violations (setup/hold, noise, crosstalk) Collaborate with design, physical design, and verifi
$32,000 – $52,000/year
Estimation confidence: Low
Estimate based on market data for San Jose. Actual salaries may vary depending on experience, company, and area.
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