Jayashree Chava

Senior Layout Designer with 25+ years of semiconductor industry experience. Deep expertise in full-chip and block-level physical layout, floor planning, placement, routing, and layout verification for advanced technology nodes. Proven history of delivering high-quality, schedule-driven designs with strong DRC/LVS closure and cross-functional collaboration under high pressure, high stress situations.

Senior Layout Designer - Intel Corporation

(1998-09)

• Coral Rapids - 14A Xeon 8P core Server processor: planning and Routing global routes like Mesh, Analog.
• Coral Rapids - 14A Xeon 8P core Server processor: full-chip layout, created full-chip analog blockages, and implemented full-chip UFI routing.
• Diamond Rapids - 18A-P Xeon 7 Server processor: congestion/pin-access closure and tape out readiness
• Diamond Rapids - 18A-P Xeon 7 Server processor: Triage designs that completed finish stage during early stages and provide feedback to reduce manual effort during final LV clean-up.
• Diamond Rapids - 18A-P Xeon 7 Server processor: FP mock0, providing feedback on base layer DRCs, identify systematic issues with flow or construction issues that PO need to address.
• Diamond Rapids - 18A-P Xeon 7 Server processor: Owned physical implementation from floorplan handoff through route completion and verification closure.
• Diamond Rapids - 18A-P Xeon 7 Server processor: Partnered with design, timing, DFT, and verification teams to close critical implementation issues.
• Sierra Forest – Xeon Gen 6 Data center processor: Owned hierarchical routing/debug and signoff-driven physical fixes across block interfaces.
• Sierra Forest – Xeon Gen 6 Data center processor: Drove congestion, pin-access, and blockage optimization to improve routability.
• Sierra Forest – Xeon Gen 6 Data center processor: Executed ECO integration and cleanup for release/signoff readiness.
• Sierra Forest – Xeon Gen 6 Data center processor: Partnered with timing/verification teams for DRC/LVS convergence and tape out closure.
• Sierra Forest – Xeon Gen 6 Data center processor: Resolved congestion, pin access, and hierarchical route handoff challenges in late-stage ECO cycles.
• Skylake - 14nm Gen 6 Core processor: Physical layout execution for top/block integration; route closure and late ECO cycles.
• Skylake - 14nm Gen 6 Core processor: Led top-level and block-level layout integration for complex CPU/SoC programs.
• Skylake - 14nm Gen 6 Core processor: Managed hierarchical connectivity, propagated pins, and interface route closure across partitions.
• Skylake - 14nm Gen 6 Core processor: Improved layout quality and schedule predictability through reusable scripts and layout checks.
• Skylake - 14nm Gen 6 Core processor: Supported tape out milestones with fast-turn ECOs and documentation.

B.S. - Mechanical Engineering - Nagpur University, Maharashtra India

Advanced Physical Design / Layout Verification