Huan Vinh
Senior Analog/RFIC Layout Engineer
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About
Strategic and results-driven Senior Analog and RFIC Layout Engineer with 20+ years of experience delivering production-ready, high-performance integrated circuits from concept and architecture through tape-out. Deep expertise across CMOS, SOI, BiCMOS, Bipolar, and advanced FinFET technologies down to 5nm. Recognized technical authority in full-chip and complex RF/analog integration, leading layout execution for LNAs, PAs, VCOs, PLLs, mixers, switches, and high-speed systems.
Expert in device matching, parasitic optimization, EM reliability, RF shielding, and high-frequency routing—consistently enabling first-pass silicon success in leading-edge nodes. Proven track record of accelerating development cycles, optimizing layout methodologies, and partnering cross-functionally to deliver mission-critical semiconductor products on schedule.
Experience
Consulting & Contract Experience – Analog / RFIC Layout Consultant - Qorvo - Greensboro, NC
(2025-01)
Consulting & Contract Experience – Analog / RFIC Layout Consultant - SpaceX - Irvine, CA
(2024-07 - 2025-08)
Led RF block layout for complete RX receiver integration in TSMC 3nm, 12nm FinFET technology. Ensured parasitic control, device matching, and high-frequency integrity to support mission-critical applications.
Consulting & Contract Experience – Analog / RFIC Layout Consultant - InnoPhase IoT Semiconductor - San Jose, CA
Delivered PA, TX_TOP, LO tree, MUX, and power capacitor array layouts. Executed optimized floorplanning and dense analog integration in TSMC 22nm process.
Consulting & Contract Experience – Analog / RFIC Layout Consultant - Qorvo - Greensboro, NC
Designed LNA and RF switch layouts using 28nm SOI (GlobalFoundries) and 90nm UMC technologies. Focused on RF performance optimization, isolation, and reliability.
Consulting & Contract Experience – Analog / RFIC Layout Consultant - Achenar Technology - San Diego, CA
Supported full analog block layouts in TSMC 16nm, FinFET process, delivering advanced-node integration with emphasis on parasitic minimization.
Consulting & Contract Experience – Analog / RFIC Layout Consultant - Qorvo - Remote
Implemented RF switch layouts in 28nm SOI and 90nm UMC processes, contributing to multiple successful production tape-outs.
Consulting & Contract Experience – Analog / RFIC Layout Consultant - Luxtera - Carlsbad, CA
Executed high-speed analog layouts in advanced FinFET nodes (5nm-class technology), addressing routing density, parasitic sensitivity, and signal integrity for advanced geometry blocks.
Senior RFIC Layout Engineer - Broadcom Limited - Irvine, CA
(2005-11 - 2016-08)
Led block-level through full-chip RFIC and analog layout development across TSMC 28nm, 40nm, 65nm, 90nm (LP/G) technologies for Bluetooth, GPS, Zigbee, NFC, 3G, and 60GHz RF products. Implemented advanced matching, shielding, and high-frequency routing strategies. Ensured EM reliability and consistent first-pass tape-outs for high-volume production.
Senior Analog Mask Designer - Motia Inc. - Newport Beach, CA
(2004-07 - 2005-11)
Designed RF and analog masks for 2GHz and 5GHz Smart Antenna chips. Delivered top-level integration including LNA, AGC amplifiers, VCO, PLL, mixers, filters, and amplifiers.
Senior Mask Designer - Micron Technology - San Jose, CA
(2001-04 - 2004-07)
Responsible for Flash memory chip layout and production mask preparation. Performed DRC/LVS verification using Hercules and Avanti Explorer and prepared full mask data for tape-out.
Mask Designer (Contract) - Conexant Systems - Newport Beach, CA
(1999-04 - 2001-04)
Delivered analog and RFIC layout across CMOS, BiCMOS, and Bipolar processes for GSM, CDMA, and DSS cordless phone SoCs.
Mask Designer - Novalog - Irvine, CA
(1998-08 - 1999-04)
Responsible for chip floor planning and layout from leaf cell to top-level tape-out.
Education
Advanced Integrated Circuit Mask Design - San Jose City College
CMOS & Bi-CMOS Semiconductor Design Expertise - MOS Drafting Institute
