Saraswathy S

To leverage my skills and expertise in FPGA/RTL design for the growth and development of the organization, while ensuring delivery of high-quality solutions and exceeding expectations through dedication and continuous learning.

Senior Project Associate (FPGA/RTL Design Engineer) at Industrial Consultancy and Sponsored Research (IITM) (2017-03 – Present)

Indigenous End-to-End 5G Testbed Project

• Proactive team leader managing functional teams to deliver projects on time
• Expert in FPGA design flow (Xilinx) – compilation, synthesis, timing analysis, debug, and implementation
• Solid experience in Static Timing Analysis, Clock Domain Crossing, and Equivalence Checking
• Leading the 700 MHz team (developing, implementing, and verifying solutions for 5G NR systems)
• Hands-on experience integrating NIOS, MicroBlaze, ARM/Zynq processors, GTX/GTH transceivers
• Strong reporting skills – weekly progress, technical documentation, and summaries
• Exhibited team's work at the Indian Mobile Congress (IMC) in 2019 and 2022

Technical Writer (Contract) at Ivesia Software Solutions Pvt. Ltd (2012-01 – 2012-05)

Contract-based technical writing position

Technical Writer – Executive at Scope e-Knowledge Center Pvt. Ltd (2007-09 – 2011-02)

Technical writing and documentation role

• Prior experience in Software Testing, Technical Writing, and Quality Analysis
• Knowledgeable in Manual Testing (Black Box), STLC, and test methodologies

M.Tech in VLSI – Sathyabama University (2013 – 2015)

BE in Electronics and Communication Engineering (ECE) – Dhanalakshmi College of Engineering (2002 – 2006)

XII in General – Guru Nanak Matri.

Higher Secondary

School (2002 – 2002)

X in General – Bethel Matriculation Higher Secondary School (2000 – 2000)