Md Abid Ali

Engineer, Hardware | Digital ASIC & Physical Design | M.Tech VLSI Design

Talent

ĀsansolMember since July 6, 2026

RTL-to-GDSII FlowFloor planningPlacement & CTSRoutingStatic Timing Analysis (STA)Physical Verification (DRC/LVS)Verilog HDLRTL DesignCadence VirtuosoXilinx VivadoTCL ScriptingASIC Design FlowDigital VLSI Design

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RTL-to-GDSII FlowFloor planningPlacement & CTSRoutingStatic Timing Analysis (STA)

About

M.Tech VLSI Design candidate (GPA: 9.13/10) at VIT with hands-on, project-based experience across the digital ASIC design flow — RTL design, floor planning, placement & CTS, routing, static timing analysis (STA), and physical verification (DRC/LVS). Proficient in Verilog HDL, Cadence Virtuoso, and TCL scripting, with a strong foundation in CMOS logic, digital VLSI design, and the RTL-to-GDSII flow. IEEE-published researcher (VLSI Design & Embedded Systems Conference 2025).

Brings 2.5+ years of industry experience in process design and systematic debugging. Seeking an Engineer (Hardware) role to apply strong analytical and problem-solving skills to SoC and ASIC development.

Experience

Programmer Analyst - Cognizant Technology Solutions - Kolkata

(2021-09 - 2024-05)

Built and optimized ETL workflows using Informatica PowerCenter for large-scale enterprise data integration, developing strong skills in process flow design, debugging, and systematic problem-solving — directly transferable to RTL debug and verification workflows.
Managed enterprise servers and maintained data quality and reliability across high-volume processing pipelines — experience that translates directly to disciplined, detail-oriented engineering execution.