Souraj S

Physical Design Engineer with hands-on experience in complete RTL-to-GDSII implementation for 14nm and 28nm technology nodes using Synopsys ICC2, PrimeTime, StarRC and Design Compiler. Skilled in Floorplanning, Power Planning, Placement, CTS, Routing, STA, Timing Closure, MCMM analysis, ECO optimization and Physical Verification. Strong understanding of congestion reduction, clock tree optimization and signoff methodologies. Seeking entry-level ASIC Physical Design opportunities.

Testing Technician at Foxconn Hon Hai (2021-08 – 2023-07)

• Performed functional testing and debugging of electronic modules.
• Developed troubleshooting, hardware debugging and analytical problem-solving skills.
• Identified and resolved hardware faults during production testing stages.
• Worked with test equipment and followed standard operating procedures for validation.
• Supported defect analysis and coordinated with production teams for issue resolution.
• Monitored test results and maintained quality standards during manufacturing flow.
• Assisted in failure analysis and root cause identification for faulty boards/modules.

B.E in Electronics & Communication Engineering – Rajiv Gandhi College of Engineering (2022 – 2025)

Diploma in Electronics & Communication Engineering – NMS Kamaraj Polytechnic College (2018 – 2020)