Srikanthreddy Gade

Detail-oriented and high-velocity VLSI Engineer with comprehensive training from Takshila Institute of VLSI Technology across RTL Design, UVM Functional Verification, Tcl Tool Automation, and Static Timing Analysis (STA). Proven capability in architecting complete UVM testbenches from scratch across 7 industry-standard interface protocols (AXI4, APB, I2C, FIFO, UART, SPI, PCIe) achieving 94–96% functional coverage closure with 120+ SVA protocol assertions. Experienced in writing custom Tcl regression scripts, implementing Clock Domain Crossing (CDC) synchronizers, and developing SDC timing constraints for setup/hold slack closure.

ASIC Design & Verification Trainee at Takshila Institute of VLSI Technology (2025-06 – 2025-11)

• Built complete UVM verification environments from scratch for verified protocols (AXI4, APB, I2C, UART, FIFO, SPI, PCIe) with custom Sequencers, Drivers, Monitors, Scoreboards, and Coverage Collectors, reaching 94–96% functional coverage closure.
• Authored 120+ SystemVerilog Assertions (SVA) for protocol rule checking and executed regression test suites up to 900K simulation cycles, isolating protocol compliance, reset timing, and register-collision bugs via root-cause debug.
• Authored custom Tcl scripts for QuestaSim and Vivado to automate batch regression runs, coverage database merging, and SDC timing checks.
• Created constrained-random sequences verifying complex corner cases: AXI4 burst modes, PCIe packet flow, I2C arbitration loss, and UART framing errors; mentored junior peers in UVM testbench and Tcl workflow setup.

Bachelor of Technology (B.Tech) in Electronics & Communication Engineering – Krishna Chaitanya Institute of Technology & Sciences (JNTUK) (2021 – 2025)

Intermediate (12th Standard) in MPC – NRI Junior College (2021 – 2021)

Secondary School Certificate (SSC / 10th) – Sri Vivekananda Vidya Peetam School (2019 – 2019)