Vinizz

Mixed-signal IC designer and postdoctoral researcher with hands-on analog/digital circuit design experience spanning ASIC tapeouts (28nm, 130nm, 180nm), CMOS device modeling and neuromorphic (SNN) hardware architecture. Delivered end-to-end silicon from schematic through fabrication-ready GDSII, including RTL synthesis, place-and-route, and DRC/LVS/RC sign-off.

Builded

Python-based PDK-to-behavioral-model simulation pipelines and PVT-aware, hardware-constrained training flows for machine learning accelerators. Strong record of peer-reviewed publications in memristive devices, echo state networks and variation-tolerant spiking neural network hardware. Seeking a full-time Analog/Mixed-Signal IC Design Engineer or Neuromorphic Hardware Engineer role.

Postdoctoral Research Associate — Analog Mixed-Signal Design at University of Maryland, College Park (2025-03 – Present)

Advisor: Prof. Sahil Shah

• Contributed to a mixed-signal SNN ASIC tapeout in a 28nm process node, covering architecture definition through fabrication handoff.
• Built Python-based simulation and modeling workflows that translate low-level silicon/PDK parameters into non-linear device models, informing hardware-constrained system behavior directly applicable to numerical/physics-based circuit simulation.
• Designed PVT-aware training pipelines that account for device non-idealities, addressing convergence and accuracy challenges comparable to DC/Transient circuit simulators.
• Executed an end-to-end ASIC tapeout flow in a 180nm process node, driving the complete physical implementation pipeline — RTL synthesis, place-and-route, and sign-off verification (DRC/LVS/RC extraction) — to produce clean, fabrication-ready GDSII layout.
• Co-instructed the graduate Mixed-Signal VLSI Design course.

Research Intern — ReRAM / Neuromorphic Devices at Indian Innovation Centre of Graphene (IICG) (2021 – 2024)

• Designed analog circuits in Cadence Virtuoso/Spectre on a 130nm process node; contributed to layout and DRC/LVS signoff.
• Researched ReRAM devices with a focus on graphene-based crossbar array materials for neuromorphic memory applications.

Ph.D. Researcher — Neuromorphic Computing at Digital University Kerala (2021-11 – 2026-02)

• Designed peripheral circuits, including ADC and SPI interfaces, for neuromorphic computing applications.
• Implemented an FPGA-based Echo State Network on the Arty A7 100T platform.

Assistant Professor — Electronics & Communication Engineering at College of Engineering Chengannur & SRI Institutions (2014-09 – 2022-08)

• Developed and delivered engineering curricula in circuit design and electronic systems; mentored undergraduate and graduate students on capstone projects and career development.
• Facilitated lab sessions and designed course materials aligned with industry standards; collaborated with faculty on instructional methodology and assessment.

Ph.D. in Electronics Engineering (Neuromorphic Computing) – Digital University Kerala (2021 – 2026)

M.E. in VLSI Design – Sri Eshwar College of Engineering (2012 – 2014)

B.Tech. in Electronics & Communication Engineering – Mount Zion College of Engineering, Kadammanitta (2008 – 2012)