Ata Bani

Analog/Mixed-Signal IC Design Engineer and Electronic Engineering Ph.D. with 7+ years of hands-on experience in precision and low-noise analog design — bandgap and voltage references, PTAT and biasing networks, LDOs and power management, op-amps, comparators, and low-noise front-ends — in advanced CMOS, from architecture through tape-out and silicon validation, with data-converter experience including capacitive DAC design and SAR ADC contribution. Strong foundation in high-speed and clocking design — PLL/DLL, oscillators (ring, LC VCO), CML and broadband building blocks, SerDes/CDR, equalization, and signal integrity — developed through graduate (Ph.D.) coursework, design projects, and continued development, complementing a deep analog foundation.

Experienced across the full design flow: transistor-level design and optimization, PVT / Monte Carlo / corner signoff, Verilog-A and mixed-signal AMS behavioral modeling, post-layout verification, and laboratory characterization. Proven track record taking analog and mixed-signal blocks from concept through tape-out, silicon bring-up, debug, and production, collaborating across layout, digital, system, and validation teams.

Senior Mixed-Signal IC Design Engineer at Nexperia (2022-01 – 2024-12)

Automotive-grade USB Type-C Power Delivery controller IC (NEX53100-Q100) integrating analog, mixed-signal, monitoring, control, protection, and timing-sensitive analog subsystems in advanced CMOS.

• Designed bandgap reference, PTAT current generation, biasing circuits, and voltage-reference subsystems for stable mixed-signal operation and analog control-loop robustness
• Developed analog front-end blocks including comparators, op-amps, and voltage references
• Designed and verified on-chip temperature sensing (NTC interface) and protection circuits (OVP/UVP)
• Contributed to a 10-bit ADC-based monitoring system, mixed-signal feedback/control loops, and timing-sensitive analog subsystems
• Verified robustness through PVT, Monte Carlo, and corner analysis, with parasitic-aware design and layout
• Participated in full-chip integration, verification, silicon evaluation, and post-silicon debug, correlating simulation to measured silicon
• Supported system-level power management and fault-protection architecture; mentored junior engineers and contributed to design-review best practices

Mixed-Signal IC Design Engineer at National Institute of Physics (INFN) (2017-01 – 2021-12)

Low-noise multi-channel readout ASIC for radiation-detector systems.

• Architected and designed a complete low-noise analog signal chain: 9th-order semi-Gaussian shaping amplifier (active filter), baseline holder, peak detector, analog multiplexer, and output buffers
• Optimized noise, linearity, dynamic range, mismatch sensitivity, and stability through transistor-level analysis, sensitivity analysis, and Monte Carlo simulation across corners
• Developed Verilog-A behavioral models for system-level verification and architectural exploration
• Performed transistor-level design, SPICE simulation, noise analysis, and system-level verification
• Led silicon characterization and laboratory validation including noise, timing, dynamic range, and spectroscopy measurements using oscilloscopes and signal generators

Mixed-Signal IC Design Engineer at Politecnico di Milano (2017-01 – 2021-12)

Integrated readout ASIC with on-chip data converter and digital interface.

• Designed the capacitive DAC and contributed to the design and integration of a 12-bit SAR ADC (comparator, SAR logic), through tape-out and lab validation
• Developed biasing circuits, op-amps, and reference generators
• Implemented data-acquisition and multiplexing architecture
• Performed mixed-signal verification, AMS simulation, and full-system validation in lab with detector interface

Ph.D. in Electronic Engineering – Polytechnic University of Milan (2017-01 – 2021-12)

Master of Science in Electronic Engineering – University of Bologna (2014-01 – 2017-12)

Bachelor of Science in Electronic Engineering – University of Bologna (2005-01 – 2011-12)