About
Advanced SOC/FPGA/AI Fabric chip design to eliminate mask tape out revision such as SerDes, PLL, LSRAM, etc.
- Advanced CMP/dry etch/wet etch processing for 12nm or below
- Advanced CMP/dry etch/wet etch for TSV for 2.5D/3D advanced packaging
- Emerging memory ReRAM, MRAM, NVM DRAM fabrication and integration
- Advanced architect and OS for robot robot in face interaction.
Experience
BRIEF SELF-INTRODUCTION
- Veteran in semiconductor industry with 20 years’ experience through journeys with Microchip, Intel, Maxim, Texas Instruments & Bell Labs/Lucent from 0.35um to 4nm.
- Foundry experience with UMC, Global Foundry, TSMC, SMIC etc.
- Expertise in R&D/MFG, foundry management for FPGA, CPU, ASIC, DSP, SOC, 3D packaging, RF/analog, embedded memory, high speed connection such as SerDes, PCle®, CXL® etc.
- Specialized in innovative process development in advanced semiconductor manufacturing: CMP, dry/wet etch, RVD, CVD, ALD thin film deposition, SORT, FT, FA etc.
- AI/Robotics professional and founded Doublewell Network Robotics for caring, education and services etc.
EMPLOYMENT HISROTY
- Microchip Technology, Foundry Technical Project Manager for G5/G6 FPGA, San Jose, CA
- Doublewell Network Robotics, President/Founder, San Jose, CA
- Intel Fab11X, SMTS, Cu CMP & STI dry etch module Process, 28/32nm CPU, Rio Rancho, NM
- DBW Microelectronics, President, RF/Analog, Dallas, TX
- Maxim Integrated Products, SMTS, CMP manager/process Integration, Analog, Dallas, TX
- Texas Instruments, MTS, Cu CMP process development, 65nm DSP, Dallas, TX
- Bell Labs/Lucent, MTS, process integration & CMP process development, 0.35/0.25/0.16um SOC DSP, Orlando, FL
Education
Ph.D. in Condensed Matter Physics, Princeton University
M.S. in Solid State Physics, Institute of Physics, Chinese Academy of Sciences
B.S. in Electrical Engineering, Nanchang University
