Meghna Kar
RTL Design Engineer (Fresher)
Talent
Chandkheda, Ahmedabad, GujaratMember since August 16, 2026
Verilog HDLXilinx VivadoRTL SimulationSynthesisArtix-7UARTSPII²CClock Domain Crossing (CDC)Asynchronous FIFOTri-state LogicFunctional Verification
·
Hire this person
Send a job offer directly to this candidate
Verilog HDLXilinx VivadoRTL SimulationSynthesisArtix-7
About
RTL Design Engineer (Fresher) specializing in Verilog HDL-based RTL development, FPGA prototyping, and functional verification. Hands-on experience designing and verifying UART, SPI, and I²C communication systems with CDC, FSM-based datapaths, and Asynchronous FIFO architectures on Artix-7 FPGA using Xilinx Vivado. Targeting RTL Design and Digital Design Engineer internship and fresher roles in VLSI and semiconductor design.
Education
B.Tech - Electronics & Communication Engineering - Institute of Engineering & Management (IEM), Kolkata (2028)
Skills
RTL Design Engineer (Fresher)
