Murali Yadav

Highly motivated and detail-oriented recent graduate with a strong foundation in digital design, VLSI, and physical design principles, seeking an entry-level position as an ASIC Physical Design Engineer. Eager to apply academic knowledge in synthesis, place and route, and timing analysis, and to gain practical experience with industry-standard EDA tools. Committed to continuous learning and contributing to the successful development of innovative ASIC designs in a collaborative, fast-paced environment.

Physical Design Engineer - Trainee - Sumedha IT - Hyderabad

• Performed block-level synthesis using DC_shell, optimizing for area, power, and timing to improve overall efficiency.
• Defined and refined synthesis constraints to enhance timing performance and meet design specifications.
• Executed placement, CTS, and routing to achieve optimal PnR results with minimal congestion and DRC violations.
• Conducted block-level PV checks such as LVS and DRC and resolved all reported violations.
• Applied partial blockages and path groups to reduce congestion and improve timing.
• Analysed and fixed setup and hold violations during both synthesis and post-routing stages.
• Successfully achieved timing closure through detailed STA and constraint tuning.

Bachelor of Technology - Electronics and Communication Engineering - Sree Dattha group of institutions (2020-03 - 2024-04)

Board of Intermediate Education - C.V Raman Junior College (2018-07 - 2020-05)