Raghavendra K S
ASIC Physical Design Engineer, Staff
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About
11+ years of strong experience in EDA tools in the field of VLSI industry.
8 years of strong experience in Physical Design using Synopsys ICC/ICC2, Fusion compiler and Cadence Innovus tools for executing designs from Netlist to GDSII with 2nm, 3nm. 5nm, 6nm, 7nm, 10nm, 12nm & 28nm technology nodes.
3 years of experience in design verification and validation.
Experience in handling High utilized and critical blocks.
Major experience in Physical design flow stages particularly in Floorplan, Placement, CTS, STA and Routing, IR drop analysis, ECO flow, Physical Verification: Cleaning DRC/LVS issues
Worked with Intel RDT flow for APR, AMD TileBuilder Flow and MediaTek, Synopsys Make Build flow for PnR. Block level Timing Closure and resolving various Block level PnR issues.
Experience on fixing flow environment related issues and changing the flow parameters according to requirements.
Worked on UCIe and HBM Phy interface IPs at advanced technology nodes.
Good Analytical Approach in design and layout problem solving. Mentored junior engineers in resolve their block level flow, technical issues and closure challenges. * Proficient in TCL scripting and Unix/Linux environment.
Experience
ASIC Physical Design Engineer, Staff at Synopsys Pvt Ltd. (2022-11 – 2026-04)
Senior Engineer at Synapse Techno Design Innovations Pvt Ltd. (2019-04 – 2022-11)
Engineer at Aricent Technologies Pvt Ltd. (2018-07 – 2019-04)
Design and Application Engineer at Trident Infosol Pvt. Ltd. (2016-03 – 2018-06)
Trainee Engineer at Sierra Circuits. (2014-08 – 2015-11)
Education
B.E in Electronics & Communication Engg. – R V College of Engineering Bangalore (2014)
Diploma in Electronics & Communication Engg. – D.A.C.G Govt. Polytechnic Chikkmagaluru (2011)
Xth Standard – GJC Kadur (2008)
