An Huynh

Expert in Layout design for Analog and Mix-Signal circuits with 10 years of experience. Proficient in designing amplifiers, comparators, bandgap references, and current sources. Strong expertise in matching, shielding, guard ring, and latch-up prevention techniques.

Experienced with industry-leading EDA tools including Cadence Virtuoso and Mentor Calibre. Deep understanding of physical effects in advanced technology nodes. Successfully contributed to multiple tape-outs on advanced technology nodes from 65nm to 4nm.

Block level/Top-level Engineer - Da Nang City - VietNam

(2024-01 - 2025-12)

LPDDR45 project on Samsung/4nm process

• Investigate floor-plan for new block
• Task assignment for member
• Layout for block: rx_dfe, xmos, cal_amplifier
• Layout for top cell: USEIO/USEO
• Layout for BYTE_LANE top
• Verify: DRC/LVS/ERC/ANT/LUP
• Setting and check EM for rx, cal_amplifier
• Run extraction to optimize Cap/Res
• Run batchmode to verify all topcell
• Make flatten/hier netlist to release
• Verify on Pad-frame
• Check PERC topo
• Gen fill and fix density for Pad-Frame with Bump

Leader - Da Nang City - VietNam

(2023-01 - 2024-12)

Technical Training for junior engineers on TSMC/12nm – Samsung/4nm processes

• Make training plan and schedule for junior engineers
• Manage and setup training data and design flow
• Layout Basics – Overview of Analog, Mixed-Signal, process nodes, and key design techniques (Matching, Shielding, Guard Ring, Latch-up Prevention)
• EDA Tools Training – Hands-on with Cadence Virtuoso, Mentor Calibre for DRC/LVS/ERC/PEX
• Practical Exercises – Layout practice for basic circuit
• Review and evaluate engineers' performance after the training

Block Level Engineer / Top-level Engineer - Da Nang City - VietNam

(2022-01 - 2023-12)

IP/DDR/LPDDR34 project on TSMC/7nm, TSMC/12nm, Samsung/28fdsoi processes

• Layout for block: Bias, vref, rx_comp, xmos, levelshifter, cal_amplifier tx
• Layout for top cell: USEIO/USEO/UDIO/Power cell
• Verify: DRC/LVS/ERC/ANT/LUP
• Run extraction to optimize Cap/Res
• Run batchmode to verify all topcell
• Make flatten/hier netlist to release
• Verify on Pad-frame
• Setting and run PERC to check ESD topo/ Current density

Block Level Engineer / Top-level Engineer - Da Nang City - VietNam

(2019-01 - 2021-12)

IP/DDR/LPDDR project on GF/22FDX, Samsung/14nm, Samsung/28fdsoi, UMC/22nm processes

• Layout for block: xmos, rx, tx, cal_amplifier, bandgap
• Layout for top cell: USEIO/USEO/UDIO/ Power cell
• Verify: DRC/LVS/ERC/ANT/LUP
• Run extraction to optimize Cap/Res
• Setting and run EMIR for rx/ cal_amplifier
• Gen dummy fill for all cell

Block Level Engineer - Da Nang City - VietNam

(2016-01 - 2018-12)

IP/DDR/LPDDR project on TSMC/16nm, TSMC/22nm, TSMC/28nm processes

• Layout for block: bias, vref, rx_comp, xmos, levelshifter, cal_amplifier tx
• Verify: DRC/LVS/ERC/ANT/LUP
• Run extraction to optimize Cap/Res

B.S. - University of Information Technology (2016)