Cheing-Ying Chen
Over 3 years of experience in semiconductor yield improvement and cross-department integration, specializing in DRAM, eFLASH, Logic, Mixed-Signal process yield and quality enhancem
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關於
Over 3 years of experience in semiconductor yield improvement and cross-department integration, specializing in DRAM, eFLASH, Logic, Mixed-Signal process yield and quality enhancement. Strong communication, planning, logical analysis, and stress resistance.
工作經歷
Product Engineer at Microchip Technology Inc. (2024-04 – Present)
Advanced Packaging
- Extensive experience in semiconductor yield, process, device, and quality improvement across NAND Flash, logic, mixed-signal, RF, high-voltage, and analog products, covering technology nodes from 28nm to 0.18μm.
- Hands-on experience collaborating with leading external foundries, including TSMC and UMC, to identify yield-loss mechanisms, develop and execute Design of Experiments (DOE), perform root-cause analysis, and implement continuous improvement programs (CIP) to enhance product yield and quality.
- Extensive collaboration experience with major OSAT partners, including ASE and GTTW, supporting assembly process development, yield optimization, and quality improvement across multiple advanced packaging technologies, including WLCSP, FinePitch FCBGA, SiP, and 2.5D Packaging.
- Experienced in driving packaging-related yield improvement and quality enhancement through cross-functional problem solving, process optimization, failure analysis, and implementation of corrective and preventive actions.
Process Integration Engineer at Micron Technology Inc. (2022-05 – 2023-08)
Advanced Packaging / HBM & DRAM Product
- Strong semiconductor engineering background in BEOL processes of DDR4/5, DRAM operation principles, statistical data analysis, and semiconductor manufacturing yield improvement.
- Hands-on experience collaborating with assembly and packaging teams to resolve cross-loop integration issues involving Fine-Pitch BGA and HBM-type products, including packaging-related quality, yield, and manufacturing challenges.
- Familiar with HBM-related packaging integration, DRAM product characteristics, and fine-pitch interconnect technologies
教育背景
Master of Science in Engineering in Biomechatronics Engineering – National Taiwan University (2019-07 – 2021-10)
Bachelor in Mechatronic Engineering – National Sun Yat-Sen University (2015-09 – 2019-06)
